s5pv210数据手册 -金沙js1005线路

s5pv210 is a 32-bit risc cost-effective, low power, and high performance microprocessor solution for mobile phones and general applications. it integrates the arm cortex-a8 core, which implements the arm architecture v7-a with supporting peripherals. to provide optimized hardware (h/w) performance for the 3g and 3.5g communication services, s5pv210 adopts 64-bit internal bus architecture. this includes many powerful hardware accelerators for tasks such as motion video processing, display control, and scaling. integrated multi format codec (mfc) supports encoding and decoding of mpeg-1/2/4, h.263, and h.264, and decoding of vc1. this hardware accelerator (mfc) supports real-time video conferencing and analog tv out, hdmi for ntsc, and pal mode. s5pv210 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in high-end communication services. the memory system has flash/ rom external memory ports for parallel access and dram port to meet high bandwidths. dram controller supports lpddr1 (mobile ddr), ddr2, or lpddr2. flash/ rom port supports nand flash, nor-flash, onenand, sram, and rom type external memory. to reduce the total system cost and enhance the overall functionality, s5pv210 includes many hardware peripherals such as tft 24-bit true color lcd controller, camera interface, mipi dsi, csi-2, system manager for power management, ata interface, four uarts, 24-channel dma, five timers, general i/o ports, three i2s, s/pdif, three (general purpose) iic-bus interfaces, two hs-spi, usb host 2.0, usb 2.0 otg operating at high speed (480mbps), four sd host and high-speed multimedia card interface, and four plls for clock generation. package on package (pop) option with mcp is available for small form factor applications.