myd-金沙js1005线路

  概述

the lpc1850fet256 is a high-performance, cost-effective cortex-m3 microcontroller featuring 200 kb of sram, and advanced peripherals including ethernet, high speed usb 2.0 host/otg/device, lcd controller, and can 2.0b. operating at speeds up to 180 mhz, the lpc1850 also features two new configurable peripherals: a spi flash interface and a state configurable timer. all members of the series include a wakeup interrupt controller allowing automatic wake from any priority interrupt as well as four reduced power modes: sleep, deep-sleep, power-down, and deep power-down.

  主要参数和优势

• arm cortex-m3 processor, running at frequencies of up to 180 mhz
• arm cortex-m3 built-in memory protection unit (mpu) supporting eight regions
• arm cortex-m3 built-in nested vectored interrupt controller (nvic)
• non-maskable interrupt (nmi) input
• jtag and serial wire debug
• etm and etb support
• system tick timer
• 200 kb sram for code and data use
• 32 kb rom containing boot code and on-chip software drivers
• crystal oscillator with an operating range of 1 mhz to 25 mhz
• 12 mhz internal rc oscillator trimmed to 1 % accuracy
• ultra-low power rtc crystal oscillator
• clock output
• two plls allow cpu operation up to the maximum cpu rate
• quad spi flash interface with four lanes and data rates of up to 40 mb/s
• 10/100t ethernet mac with rmii and mii interfaces and dma support
• one high-speed usb 2.0 host/device/otg interface with dma support
• one high-speed usb 2.0 host/device interface with dma support
• four 550 uarts with dma support: one uart with full modem interface
• one uart with irda interface
• one c_can 2.0b controller with one channel
• two ssp controllers with fifo and multi-protocol support
• one fast-mode plus i2c-bus interface with monitor mode
• one standard i2c-bus interface with monitor mode and standard i/o pins
• one i2s interface with dma support and with one input and one output
• external memory controller (emc)
• sd/mmc card interface
• eight-channel general-purpose dma (gpdma) controller
• up to 164 general-purpose input/output (gpio) pins
• gpio registers are located on the ahb for fast access
• state configurable timer (sct) subsystem on ahb
• four general-purpose timer/counters with capture and match capabilities
• one motor control pwm for three-phase motor control
• one quadrature encoder interface (qei)
• repetitive interrupt timer (ri timer)
• windowed watchdog timer
• ultra-low power real-time clock (rtc) on separate power domain
• alarm timer; can be battery powered
• one 10-bit dac with dma support and a data conversion rate of 400 ksamples/s
• two 10-bit adcs with dma support and a data conversion rate of 400 ksamples/s
• hardware-based aes security engine programmable through an on-chip api
• two 128-bit secure otp memories for aes key storage and customer use
• unique id for each device
• single 3.3 v (2.2 v to 3.6 v) power supply with on-chip voltage regulator
• rtc power domain can be powered separately by a 3 v battery supply
• four reduced power modes
• overdrive mode to increase cpu and bus clock frequency
• processor wake-up from sleep mode via wake-up interrupts
• wake-up from deep-sleep, power-down, and deep power-down modes
• brownout detect with four separate thresholds for interrupt and forced reset
• power-on reset (por)

  应用

• industrial
• consumer
• white goods
• rfid readers
• e-metering

  产品参数