myd-金沙js1005线路

  概述

the lpc4350fet256 is an arm cortex-m4 based digital signal controller with an arm cortex-m0 coprocessor designed for embedded applications requiring signal processing. the arm cortex-m4 core offers single-cycle multiply-accumulate and simd instructions and a hardware floating-point unit to support signal processing while the m0 coprocessor handles i/o and digital control processing. the lpc4350fet256 includes 264 kb of data memory, two high speed usb 2.0 host/otg/devices, advanced configurable peripherals such as the state configurable timer (sct), serial general purpose i/o (sgpio), and spi flash interface (spifi) as well as ethernet, lcd, an external memory controller and multiple digital and analog peripherals.

  主要参数和优势

• arm cortex-m4 processor, running at frequencies of up to 204 mhz
• arm cortex-m4 built-in memory protection unit (mpu) supporting eight regions
• arm cortex-m4 built-in nested vectored interrupt controller (nvic)
• hardware floating-point unit
• non-maskable interrupt (nmi) input
• jtag and serial wire debug (swd)
• system tick timer
• arm cortex-m0 co-processor running at frequencies of up to 204 mhz
• 264 kb sram for code and data use
• two 32 kb sram blocks with separate bus access
• 32 kb rom containing boot code and on-chip software drivers
• 32 bit one-time programmable (otp) memory for customer use
• serial gpio (sgpio) interface
• state configurable timer (sct) subsystem on ahb
• quad spi flash interface (spifi) with four lanes and up to 40 mb per second
• 10/100t ethernet mac with rmii and mii interfaces and dma support
• one high-speed usb 2.0 host/device/otg interface with dma support
• one high-speed usb 2.0 host/device interface with dma support
• one 550 uart with dma support and full modem interface
• three 550 usarts with dma and synchronous mode support
• one c_can 2.0b controller with one channel
• two ssp controllers with fifo and multi-protocol support
• one spi controller
• one fast-mode plus i2c-bus interface with rates of up to 1 mbit/s
• one fast-mode i2c-bus interface
• two i2s interfaces
• external memory controller (emc) supporting external sram, rom, flash, sdram
• lcd controller with dedicated dma controller and a selectable display resolution
• secure digital input output (sdio) card interface
• eight-channel general-purpose dma (gpdma) controller
• up to 164 general-purpose input/output (gpio) pins
• four general-purpose timer/counters with capture and match capabilities
• one motor control pulse width modulator (pwm) for three-phase motor control
• one quadrature encoder interface (qei)
• repetitive interrupt timer (ri timer)
• windowed watchdog timer (wwdt)
• ultra-low power real-time clock (rtc) on separate power domain
• alarm timer; can be battery powered
• one 10-bit dac with dma support and a data conversion rate of 400 ksamples/s
• two 10-bit adcs with dma support and a data conversion rate of 400 ksamples/s
• two 128-bit secure otp memories for aes key storage and customer use
• crystal oscillator with an operating range of 1 mhz to 25 mhz
• 12 mhz internal rc (irc) oscillator trimmed to 1 % accuracy
• ultra-low power real-time clock (rtc) crystal oscillator
• three plls allow cpu operation up to the maximum cpu rate
• clock output
• single 3.3 v (2.2 v to 3.6 v) power supply with on-chip dc-to-dc converter
• rtc power domain can be powered separately by a 3 v battery supply
• four reduced power modes
• processor wake-up from sleep mode via wake-up interrupts
• brownout detect with four separate thresholds for interrupt and forced reset
• power-on reset (por)
• see selection guide for features per type

  应用

• industrial
• consumer
• white goods
• rfid readers
• e-metering

  产品参数