at91sam9g45数据手册 -金沙js1005线路

features • 400 mhz arm926ej-s™ arm® thumb® processor – 32 kbytes data cache, 32 kbytes instruction cache, mmu • memories – dual external bus interface supporting 4-bank ddr2/lpddr, sdram/lpsdr, static memories, compactflash, slc nand flash with ecc – one 64-kbyte internal sram, single-cycle access at system speed or processor speed through tcm interface – one 64-kbyte internal rom, embedding bootstrap routine • peripherals – lcd controller supporting stn and tft displays up to 1280*860 – itu-r bt. 601/656 image sensor interface – usb device high speed, usb host high speed and usb host full speed with on- chip transceiver – 10/100 mbps ethernet mac controller – two high speed memory card hosts (sdio, sdcard, mmc) – ac'97 controller – two master/slave serial peripheral interfaces – two three-channel 32-bit timer/counters – two synchronous serial controllers (i2s mode) – four-channel 16-bit pwm controller – two two-wire interfaces – four usarts with iso7816, irda, manchester and spi modes – 8-channel 10-bit adc with 4-wire touch screen support • system – 133 mhz twelve 32-bit layer ahb bus matrix – 37 dma channels – boot from nand flash, sdcard, dataflash® or serial dataflash – reset controller with on-chip power-on reset – selectable 32768 hz low-power and 12 mhz crystal oscillators – internal low-power 32 khz rc oscillator – one pll for the system and one 480 mhz pll optimized for usb high speed – two programmable external clock signals – advanced interrupt controller and debug unit – periodic interval timer, watchdog timer, real time timer and real time clock • i/o – five 32-bit parallel input/output controllers – 160 programmable i/o lines multiplexed with up to two peripheral i/os with schmitt trigger input • package – 324-ball lfbga, pitch 0.8 mm