at91sam9x25数据手册 -金沙js1005线路

features • core – arm926ej-s™ arm® thumb® processor running at up to 400 mhz @ 1.0v /- 10% – 16 kbytes data cache, 16 kbytes instruction cache, memory management unit • memories – one 64-kbyte internal rom embedding bootstrap routine: boot on nand flash, sdcard, dataflash® or serial dataflash. programmable order. – one 32-kbyte internal sram, single-cycle access at system speed – high bandwidth multi-port ddr2 controller – 32-bit external bus interface supporting 8-bank ddr2/lpddr, sdr/lpsdr, static memories – mlc/slc nand controller, with up to 24-bit programmable multi-bit error correcting code (pmecc) • system running at up to 133 mhz – power-on reset cells, reset controller, shut down controller, periodic interval timer, watchdog timer and real time clock – boot mode select option, remap command – internal low power 32 khz rc and fast 12 mhz rc oscillators – selectable 32768 hz low-power oscillator and 12 mhz oscillator – one pll for the system and one pll at 480 mhz optimized for usb high speed – twelve 32-bit-layer ahb bus matrix for large bandwidth transfers – dual peripheral bridge with dedicated programmable clock for best performance – two dual port 8-channel dma controllers – advanced interrupt controller and debug unit – two programmable external clock signals • low power mode – shut down controller with four 32-bit battery backup registers – clock generator and power management controller – very slow clock operating mode, software programmable power optimization capabilities • peripherals – usb device high speed, usb host high speed and usb host full speed with dedicated on-chip transceiver – two 10/100 mbps ethernet mac controllers – two high speed memory card hosts – two can controllers – two master/slave serial peripheral interface – two three-channel 32-bit timer/counters – one synchronous serial controller – one four-channel 16-bit pwm controller – three two-wire interfaces – four usarts, two uarts – one 12-channel 10-bit analog-to-digital converter – soft modem • i/o – four 32-bit parallel input/output controllers – 105 programmable i/o lines multiplexed with up to three peripheral i/os – input change interrupt capability on each i/o line, optional schmitt trigger input – individually programmable open-drain, pull-up and pull-down resistor, synchronous output • package – 217-ball bga, pitch 0.8 mm