lpc18xx数据手册（包括lpc1850/lpc1830/lpc1820/lpc1810） -金沙js1005线路

the lpc18xx are arm cortex-m3 based microcontrollers for embedded applications.the arm cortex-m3 is a next generation core that offers system enhancements such aslow power consumption, enhanced debug features, and a high level of support block

integration.

the lpc18xx operate at cpu frequencies of up to 180 mhz. the arm cortex-m3 cpu incorporates a 3-stage pipeline and uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. the arm cortex-m3 cpu also includes an internal prefetch unit that supports speculative branching.

 the lpc18xx include up to 200 kb of on-chip sram data memory (flashless parts) or up to 136 kb of on-chip sram and up to 1 mb of flash (parts with on-chip flash), a quad spiflash interface (spifi), a state configurable timer (sct) subsystem, two high-speed usb controllers, ethernet, lcd, an external memory controller, and multiple digital and

analog peripherals.

remark: this user manual describes parts lpc1850/30/20/10 (flashless parts) and provides a preliminary description of the flash-based lpc18xx parts.

processor core

– arm cortex-m3 processor, running at frequencies of up to 180 mhz.

– arm cortex-m3 built-in memory protection unit (mpu) supporting eight regions.

– arm cortex-m3 built-in nested vectored interrupt controller (nvic).

– non-maskable interrupt (nmi) input.

– jtag and serial wire debug, serial trace, eight breakpoints, and four watch points.

– etm and etb support.

– system tick timer.

on-chip memory (flashless parts lpc1850/30/20/10)

– up to 200 kb sram total for code and data use.

– two 32 kb sram blocks with separate bus access. both sram blocks can be

powered down individually.

– 64 kb rom containing boot code and on-chip software drivers.

– 32 bit one-time programmable (otp) memory for general-purpose customer use.

on-chip memory (parts with on-chip flash)

– up to 1 mb total dual bank flash memory with flash accelerator.

– in-system programming (isp) and in-application programming (iap) via on-chip

boot loader software.

– up to 136 kb sram for code and data use.

– two 32 kb sram blocks with separate bus access. both sram blocks can be

powered down individually.

– 64 kb rom containing boot code and on-chip software drivers.

– 32 bit one-time programmable (otp) memory for general-purpose customer use.

clock generation unit

– crystal oscillator with an operating range of 1 mhz to 25 mhz.

– 12 mhz internal rc oscillator trimmed to 1 % accuracy.

– ultra-low power rtc crystal oscillator.

– three plls allow cpu operation up to the maximum cpu rate without the need for

a high-frequency crystal. the second pll is dedicated to the high-speed usb, the

third pll can be used as audio pll.

– clock output.

serial interfaces:

– quad spi flash interface (spifi) with 1-, 2-, or 4-bit data at rates up to 40 mb per

second.

– 10/100t ethernet mac with rmii and mii interfaces and dma support for high

throughput at low cpu load. support for ieee 1588 time stamping/advanced time

stamping (ieee 1588-2008 v2).

– one high-speed usb 2.0 host/device/otg interface with dma support and

on-chip phy.

– one high-speed usb 2.0 host/device interface with dma support, on-chip

full-speed phy and ulpi interface to external high-speed phy.

– usb interface electrical test software included in rom usb stack.

– four 550 uarts with dma support: one uart with full modem interface; one

uart with irda interface; three usarts support synchronous mode and a smart

card interface conforming to iso7816 specification.

– two c_can 2.0b controllers with one channel each.

– two ssp controllers with fifo and multi-protocol support. both ssps with dma

support.

– one fast-mode plus i2c-bus interface with monitor mode and with open-drain i/o

pins conforming to the full i2c-bus specification. supports data rates of up to

1 mbit/s.

– one standard i2c-bus interface with monitor mode and standard i/o pins.

– two i2s interfaces with dma support, each with one input and one output.

digital peripherals:

– external memory controller (emc) supporting external sram, rom, nor flash,

and sdram devices.

– lcd controller with dma support and a programmable display resolution of up to

1024h 768v. supports monochrome and color stn panels and tft color

panels; supports 1/2/4/8 bpp clut and 16/24-bit direct pixel mapping.

– sd/mmc card interface.

– eight-channel general-purpose dma (gpdma) controller can access all

memories on the ahb and all dma-capable ahb slaves.

– up to 164 general-purpose input/output (gpio) pins with configurable

pull-up/pull-down resistors and open-drain modes.

– gpio registers are located on the ahb for fast access. gpio ports have dma

support.

– state configurable timer (sct) subsystem on ahb.

– four general-purpose timer/counters with capture and match capabilities.

– one motor control pwm for three-phase motor control.

– one quadrature encoder interface (qei).

– repetitive interrupt timer (ri timer).

– windowed watchdog timer.

– ultra-low power real-time clock (rtc) on separate power domain with 256 bytes

of battery powered backup registers.

– event recorder with 3 inputs to record event identification and event time; can be

battery powered. the event recorder is available on parts with on-chip flash only.

– alarm timer; can be battery powered.

digital peripherals available on flash-based parts lpc18xx only:

– event monitor in the rtc power domain.

analog peripherals:

– one 10-bit dac with dma support and a data conversion rate of 400 ksamples/s.

– two 10-bit adcs with dma support and a data conversion rate of 400 ksamples/s.

security (lpc18sxx parts only):

– hardware-based aes security engine programmable through an on-chip api.

– two 128 bit secure otp memories for aes key storage and customer use.

– random number generator (rng) accessible through aes api.

unique id for each device.

power:

– single 3.3 v (2.2 v to 3.6 v) power supply with on-chip internal voltage regulator

for the core supply and the rtc power domain.

– rtc power domain can be powered separately by a 3 v battery supply.

– four reduced power modes: sleep, deep-sleep, power-down, and deep

power-down.

– processor wake-up from sleep mode via wake-up interrupts from various

peripherals.

– wake-up from deep-sleep, power-down, and deep power-down modes via

external interrupts and interrupts generated by battery powered blocks in the rtc

power domain.

– brownout detect with four separate thresholds for interrupt and forced reset.

– power-on reset (por).

available as 144-pin and 208-pin lqfp packages and as 100-pin, 180-pin, and

256-pin lbga packages.