dstream 仿真器系统和接口设计参考手册 -金沙js1005线路

arm ds-5 arm dstream system and interface design reference

chapter 1 conventions and feedback

chapter 2 arm dstream system design guidelines

2.1 using adaptive clocking to synchronize the jtag port ........................................... 2-2
2.2 reset signals ........................................................................................................... 2-5
2.3 arm reset signals .................................................................................................... 2-6
2.4 dstream reset signals .......................................................................................... 2-7
2.5 example reset circuits .............................................................................................. 2-8
2.6 asic guidelines ....................................................................................................... 2-9
2.7 ics containing multiple devices ............................................................................. 2-10
2.8 boundary scan test vectors ................................................................................... 2-11
2.9 pcb guidelines ...................................................................................................... 2-12
2.10 pcb connections ................................................................................................... 2-13
2.11 target interface logic levels ................................................................................... 2-14

chapter 3 arm dstream target interface connections

3.1 signal descriptions ................................................................................................... 3-2
3.2 jtag port timing characteristics .............................................................................. 3-3
3.3 serial wire debug .................................................................................................... 3-5
3.4 swd connections .................................................................................................... 3-6
3.5 swd timing requirements ........................................................................................ 3-7
3.6 trace signals ........................................................................................................... 3-8
3.7 target connectors supported by dstream ......................................................... 3-10
3.8 mictor 38 ................................................................................................................ 3-11
3.9 arm jtag 20 ........................................................................................................ 3-15
3.10 ti jtag 14 ............................................................................................................ 3-18
3.11 arm jtag 14 ........................................................................................................ 3-21
3.12 coresight 10 .......................................................................................................... 3-24
3.13 coresight 20 .......................................................................................................... 3-26
3.14 mipi 34 .................................................................................................................. 3-29
3.15 i/o diagrams .......................................................................................................... 3-33
3.16 voltage domains .................................................................................................... 3-36
3.17 series termination .................................................................................................. 3-37

chapter 4 arm dstream user i/o connections

4.1 the user i/o connector ........................................................................................... 4-2

chapter 5 designing the target board for tracing with arm dstream

5.1 overview of high-speed design ............................................................................... 5-2
5.2 pcb track impedance .............................................................................................. 5-3
5.3 signal requirements ................................................................................................. 5-4
5.4 probe modeling ........................................................................................................ 5-5